JACKSON ROBERTSON
Electrical and Computer Engineer
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GitHub LinkedIn

Digital IC & VLSI engineer focused on RTL to physical design.

Verilog RTL Digital IC Design CMOS / VLSI Timing Analysis Synthesis & P&R Cadence Genus Cadence Innovus Cadence Xcelium
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Jackson Robertson
B.S. Electrical and Computer Engineering B.S. ECE '26
M.Eng. Electrical and Computer Engineering M.Eng. ECE '27
Digital CMOS / VLSI
8-Bit Serial CMOS Multiplier
Designed an 8-bit serial-input, serial-output multiplier in 0.13 µm CMOS. Implemented 4×4 multiplier, shift register, FSM controller, and adder modules in structural Verilog. Verified module and system functionality in Cadence Xcelium/SimVision, then completed synthesis in Genus, place-and-route in Innovus, and power, performance, and area analysis.
Verilog Cadence Genus Cadence Innovus
Analog / CMOS Design
Two-Stage CMOS Operational Amplifier
Designed a two-stage single-ended CMOS operational amplifier with Miller compensation in a 0.18µm process. Implemented differential input stage, current mirror biasing, and frequency compensation. Verified gain, phase margin, and transient response using Cadence simulations.
Cadence CMOS Analog IC
Embedded Systems / Aerospace
UAV Radio Repeater for Search & Rescue
Custom quadcopter system designed to extend communication range for SAR operations, integrating RF repeater payload and mission-optimized flight platform.
RF UAV
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